Decoding device



Feb. 26, 1963 R. B. JoHNsoN DECODING DEVICE Filed Aug. 23, 195'? hv QN.kkbb Sum.

@Mk bbb INV ENTOR. REY/VLD B. JOHNSON Mja 1 Tram/EY 3,679,594 PatentedFeb. 26, 1963 3,@79594 DECQING DEVICE Reynold B. Johnson, Palo Alto,Caiif., assigner to International Business Machines Corporation, NewYork, NY., a corporation of New York Filed Aug. 23, 1957, Ser. No.679,35) 8 Claims. (Cl. 34e-174.1)

The present invention pertains generally to decoding devices and relatesmore particularly to a table lookup device for converting informationfrom one form to another.

The embodiment of the invention disclosed herein is directed tostructure for converting addresses of stored data from one form toanother, although it will he understood -that the invention should notbe limited to this use. Many other applications wherein it is desired toconvert information from one form to another on a table lookup basiswill become obvious to those skilled in the art.

Access to selected data stored in any memory device requires specificinformation regarding the location of the data within the memory. Thisinformation is referred to herein as the internal address of theselected data, and when ythe memory is supplied with the internaladdress,

access to the selected data is readily obtained. A problem identified bysuch an external address, it is necessary to' convert the externaladdress to the corresponding internal address before the data can belocated in the memory.

An object of the invention, therefore, is to provide an improved tablelookup device.

Another object is -to provide a new and improved device for convertingdata from one form to another.

A further object is to provide structure for converting an externaladdress to a corresponding internal address for obtaining access to datastored according to the i11- ternal address and defined by the externaladdress.

According to the invention, the various external addresses utilized inconnection with a given sys-tem are stored in a memory, the relatedinternal addresses also Vbeing stored in a memory in locationscorresponding to the locations of the related external addresses. Meansare provided for scanning external and internal address storagelocations simultaneously for detecting stored addresses. When suppliedwith an external address to be converted, the supplied address iscompared with the various detected external addresses and a resultingcornparison controls the selection of the corresponding internaladdress.

Thus, a further object is to provide a device for determining aninternal address according to the storage location of the correspondingsexternal address.

Still another object is to provide a system wherein external addressesare stored in locations corresponding to the storage locations of therelated internal addresses and internal addresses are determinedaccording to comparisons between supplied and stored external addresseswhile scanning the internal and external address storage locationssimultaneously.

A further object is to provide a device wherein internal and relatedexternal addresses are stored in corresponding locations in a memory andthe location of a predetermined internal address is determintedaccording to the location of the corresponding external address.

If., upon completion of the scanning operation, no external address isdetected which corresponds to an external address to be converted, i.e.,if the address to be converted is a new address for which decodingprovisions have not been made, it is necessary to update or extend thetable. To this end, new addresses are entered in storage serially bylocation as they occur and means are provided for recording the locationof the next blank address storage location for controlling the entry ofthe next new address therein. Thus, when an external address is enteredfor conversion and it is found that this address is a new one, theinvention is arranged to determine the associated internal address andto enter these addresses in corresponding blank storage locations forcontrolling future conversion operations.

A still further object, therefore, is to provide a table lookup devicehaving provisions for extending the table.

Another object is to provide a device of the type described fordetermining new external addresses.

Still another object is to provide an address conversion device whereinsupplied external addresses are compared with stored external addressesand new external addresses are entered in storage according to thecondition of a new address indicating register and under the control ofa failure-to-compare signal.

Other objects of the invention will be pointed out in the followingdescription and claims and illustrated in the accompanying drawing,which discloses, by way of exam ple, 'the principle of the invention andthe best mode which has ibeen contemplated of applying that principle.

The drawing discloses a system block diagram of an embodiment of thedecoding device of the invention.

Although the disclosed embodiment of the invention is arranged foroperation in connection with a s-torage device such as that shown anddescribed in the copending U.S. application for Letters Patent, SerialNo. 584,705, tiled May 14, 1956, in the name of Jacob J. Hagopian, nowU.S. Patent No. 3,007,144 issued October 31, 1961, the teaching of theinvention permits the application of many other types of storage and theinvention should not be limi-ted to the storage device shown.

Referring now to the drawing, the storage medium comprises a magneticdisc file 10 which includes a plurali-ty of discs 11 mounted forrotation on a suitably supported shaft 12 which is driven by a motor 13in any convenient manner. A plurality of magnetic transducers 14 areprovided for cooperating with the planar surfaces of the correspondingdiscs 11, one such transducer 14 being provided for each disc face. Eachtransducer is supported by a corresponding arm 15 and the various armsare secured to a shaft 16, the radial position of which is controlled bya positioning mechanism 17 to position the arms 15 and transducers 14adjacent selected portions of the discs 11.

Each disc face include a number of concentric data storage tracks spacedradially thereon for recording data, and access to selected tracks isobtained by furnishing a suitable internal address to a converter 18.The converter 18 may include a register or the like for storing theinternal address information, and at an appropriate time, i.e., when aswitch 19 is operated, it connects through the normally open,hereinafter referred to as n/o, a contacts of this switch to thepositioning mechanism 17 for controlling it to position the -transducersto the track correspending to the internal address then present in theconverter 13.

In addition to indicating the track to which the various transducers areto be positioned for reading or recording data, an internal address mayalso indicate the disc containing the track as well as the desiredportion of that track where serial operation is desired. When paralleloperation is utilized, -the internal address may indicate a particularstorage position on each of the various tracks. 1n either case, thisadditional information is taken from the converter 18 via -a line 20 forcontrolling suitable select-ion circuitry (not shown).

One of the discs 11, such as the disc 11a, is provided for con-trollingsystem timing. This disc contains a conventional clock trackV whichyields signals dening the various storage posi-tions on the varioustracks of the several discs. These signals are Vtaken from an associatedtransducer via a Yline 21 to an amplier 22, the amplified clock signalsbeing entered on a line 23. Also recorded lon Ythe disc 11a is aso-called reference mark which provides a signal once each discrevolution for indicating the Ibeginning of --the data recorded on thevarious d iscs, and all timing -i's-referenced to this signal. Thereference mark-is connected =by a line 24 to the input of an amplifier-25 and,-when amplified, is entered on a line 26 for use as will ybedescribed. w Y i Y According -to the-present invention, one or moretracks o f each disc -1-1 are provided for storing `the various externaland corresponding internal addresses. These addresses are recorded inparallel, the various signals which -dene -a given external address andthe corresponding internal address being recorded in c orespondingstorage llocations -of corresponding tracks on each of the variousdiscs. In this way the various signals defining a given external-address and the corresponding internal address are sensedsimultaneously via the transducers 14. Thus, that-portion of storageutilized -for decoding purposes is divided -into-two groups, Vone-forstoring external addresses and the other for-storing the correspondinginternal addresses. Any --portions of the discs 11 not used for decodingpurposes `may -be used for general storage. To determine r.an internaladdress corresponding to a -given external address, the various externaladdress storage locations-are scanned and the internal address signalssensed at the time a given external address is detected determine theinternal address.

The -decoding or address conversion Operation isjinitiated-by a s can signalapplied-to the switch 19 and to a Yscan control circuit 28 via -aline-29. Ihe scan signal indicates that an external address has beenentered into an external address register 30 -via -a line 31 and thatthe operation for converting the entered -external vaddress A-to thecorresponding internal address `-is to be initiated. 'This-signal isarranged to -operate the switch 19 -for p lae- -i-n-g iitsY a contactsin-the condition shown in the draw-ing, `thereby connecting the outputof Ithe -scan control circuit 28 through these contacts to thepositioning mechanism 17. -Means fare provided Within the scan controlcircuit v28 :for controlling the positioning mechanism17 to -posi- 'tionthe various transducers at the track containing the v'various-externaladdressesand corresponding internal ad- 4"dresses,'-if one track isutilized -for this purpose, or at the -iirst of the -several tracks-containing these addresses. In `the-'latterlinstance means arealso-provided within the lcontrol circuit 28 for controllingthepositioning mechanism -to-step to'the next track containingfthe-external addresses -up-on completion of the scan of each suchtrack. vIn the `-presentdescription-it will be assumed that-but -onetrack is lutilized for storing vthe various external addresses,

-fand in 'this case -the -external Yaddress -scan control -cirycuit2'8-need -only controlthe positioning of the trans- -ducers lat that:track in `response to the scan signal.

.Duringtavscanning operation a .relay 32 (not-shown -1in fthe-drawing)is operated for transferring its various -fcontacts 'a. through Ax.

is operated. The read amplifiers associated withl the ex- `tracksconnect through transferredn/o contacts of .the

Vrelay32 tothe read ampliiers 33, the transducers associfated with the.internal ,address tracks jbeing connected These contacts-connect Vthetrans- 35 -ucersl14 to corresponding, read. amplifiers when relay32 4through transferred n/o contacts of this relay to the amplitiers 34.

As mentioned previously, the external address is entered into theregister 30 and the condition of this register is arranged to determineone input to an external address comparator 35. The second input to thecomparator is taken from the read amplifiers 33, and when the signalstaken from the output of the read ampliiiers 33 compare with thecondition of the register 3 0, a comparison signal is generated on aline -36 taken from the comparator 35. Thus, the line 36 goes up when acomparison is made. It should also be pointed out at this 'time that aslon-g as there -has been no comparison, a line 37 connected -to theoutput of the comparator-35 is high, this line -being controlled `todrop in potential when a comparison is made.

The line 36 connects through a gating circuit 3 8 toa line 42 undercontrol of thecondition o f a bistable-trigger 39. I he trigger 39controls the potential of a line 40 connected to the gate 38. line is-high when a scanning operation is initiated since the scan l signalgates reference mark signals Lin a gate 41 -for operating -the` trigger`39. Thus, the -line 40 goes up at -t-he -beginning of the scanningoperation for gating comparison signals -t'o the line 4 2. The signalentered on theline 42 visutilized to gate -the signals vfrom .the -readamplifiers n3 4 int a buffer register 43. The output of the amplifiers 34 connects through a gate 44 to the register 43 under con- -trol of thecomparison signal, and when this signal is entered on the line 42, thesignals taken from the'amplitiers 34 are entered into the registers 43-for recording the internal address corresponding to the externaladdress -than present-in the external address register 30.

The register 43 connects to the `convex-ter 1.8 for oper- -ating thepositioning mechanism 17 in accordance with the internal address whenthe switch 19 is operated. '-I-'he line v42 connects l`to this switchfor transferring its a con- -tacts to connect the -positioning mechanismtherethrough to lthe converter 1-8. Thus, the comparison `signal entersthe appropriate internal address into the register .43 and also-operatesthe switch 19 to permit-control of -the positioning mechanism17 according to -the condition of the register 43, thereby positioningthe various transducers to the tracks defined by the address stored inthe vregister the condition of the register 30 for controlling thePQSitioning mechanism V17 to position the transducers at the appropriatetracks. The trigger 39 and the buier register 43 are reset by areset-signal applied thereto via a line 45. The reset signal may begenerated in any Aconvenient manner and is applied to the line 45 atsome time prior to the occurrence -of-the scan signal entered on the-line 29 `for resettingthe trigger 39 and `register 43 prior to -theconversion operation.

It will be recalled that means are provided for lentering new externaladdresses and the appropriate :internal address into the-system. Whenloading the address storage locations with the external-and internaladdress data, .-the locations are utilized ser-ially,the next blankaddress storage location being indicated Vby the condition of aninternal .address registerf46. Additionally, a counter 47, operated byclock pulses taken from-thefline 2-3 and by reference marks takenfromlthe line 26, is provided --for indicating the storage locationslbeing scanned and lis -also rarranged to raise the potential of a carryline 53 when -all storage locations have been scanned. "Thecondition ofthe internal Yaddress register 46 is continuously compared in aninternal address comparator circuit 48 with the condition of the counter47, and when there is a comparison a line 49 connected-from thecomparator 48 rises. Ihis signal connects throughV a gate 50 toV ajline5,1 if, and only if, the rio-comparison line 37 as Well as a line 52 ishigh. The line 37, it will 'oe recalled, is high as l'ong as there hasbeen no comparison determined by the comparator 35. The line 52 goes upif the trigger 39 has been operated and the counter has carried, therebyindicating that the various address storage locations have all beenscanned. This is true since the carry line 53 taken from the counter 47connects through a gate 54, controlled by the trigger 39, to the lineS2. Therefore, if the scanning operation has been completed, the line 52rises. If also no comparison has been determined by the external addresscomparator 35, the line 37 is high and the compare signal generated bythe internal address comparator 48 passes through the gate 59 to theline 51.

The line 51 connects to a write pulse generator 55 as well as through adelay 56 to the internal address register 46 for advancing this registerto indicate the next blank address storage location. It should be notedat this time that the aforementioned relay 32 (not shown) is deenergizedif there is no comparison in the comparator 35 during a scanningoperation. This is accomplished in any convenient manner such as by thesignal tak-en from the line 51. At any rate, the various contacts of therelay 32 are transferred to their normally closed, referred tohereinafter as n/c condition if no comparison is indicated. The outputof the Write pulse generator 55 connects through an external addresswrite matrix 57 and through n/c contacts of the relay 32 tocorresponding transducers associated with the external address discs.The condition of the write matrix 57 is controlled according to theexternal address stored in the register 30. The 'output of the writepulse generator 55 also connects through an internal address writematrix 58 and through n/ c contacts of the relay 32 to the transducersassociated with the internal address discs for controlling the entry ofthe appropriate internal address in storage, the matrix 58 being undercontrol of the internal address register 46. Thus, when the internaladdress compare signal is entered on the line 51, the new externaladdress and the corresponding internal address are entered in theappropriate storage loca-tions determined by the register 46, thisregister being advanced to indicate the next blank storage locationafter a suitable delay.

In operation the reset signal is first applied to the line 45, therebyresetting the trigger 39 and the butter register 43. Next, the externaladdress is entered into the external address register 3i) and the scansignal is applied to the line 29 for operating the switch 19l and forcausing the scan control circuit 28 to operate the positioning mechanism17 to position the transducers at the track containing the addressStor-age locations. The scan signal additionally primes the gate 41, andthe first reference mark to occur thereafter passes through this gateand operates the trigger 39. This opens both of the gates 3S and 54. lfa comparison in the external address comparator 35 occurs after the gate38 is opened, the compare signal is taken via the line 36 through thegate 33 to the line 42 for operating the switch 19 and for opening thegate 44 to permit the entry of the internal address signals taken fromthe amplifiers 34 into the butter register 43 for controlling thepositioning of the various transducers at the tracks defined by -thesesignals.

If there Ihas been no comparison upon completion of the scan, the lines37 and 52 are high and the internal address comparison signal taken fromthe line 49 passes through the gate 5G to the line 51. This signalcauses the recordation of the external address then present in theregister 3i) as Well as the internal address then present in theregister 45 in the appropriate storage locations. The signal entered onthe line 51 also causes the register 46 to be advanced to indicate thenext blank address storage location. Thus, the circuitry of theinvention is arranged to determine internal addresses corresponding toexternal addresses entered in the register 3% and then to position thevarious transducers d at the determined internal address. Additionally,if a new external address is entered into the system, i.e., an addressnot provided for previously, the circuitry is arranged to generate a`signal for entering the new external address together with thecorresponding internal address in the appropriate storage locations onthe various discs.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to the preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in the artwithout departing from the spirit of the invention. It is the intention,therefore, to be limited only as indi#- cated by the scope of thefollowing claims.

What is claimed is:

1. A storage device wherein external addresses are provided forcontrolling access to selected general storage locations defined -bycorresponding in-ternal addresses, said storage device comprising afirst portion having a plurality of storage locations for storingexternal address signals, a second portion -having a plurality oflstorage locations for storing internal address signals corresponding tostored external address signals, a third portion having a plurality ofgeneral storage locations defined by corresponding internal addresses,transducer means for detecting signals stored in said locations, meansfor controlling said transducer means to detect correspond'- ing addresssignals stored in said first and second portions simultaneously, meansresponsive to said transducer means for recognizing predetermineddetected external address signals, and means responsive to saidrecognizing means for controlling direct access by said transducer meansto a selected storage location in said third portion according todetected internal address signals corresponding to said predeterminedexternal address signals.

2. A storage device wherein external addresses are provided fordirecting access to selected general storage locations defined bycorresponding internal addresses, said storage device comprising a rstportion having a plurality `of locations for storing signalsrepresentative of external addresses, a second portion having aplurality of locations for storing signals representa-tive of internaladdresses corresponding to stored external addresses, a third portionhaving a plurality of general storage locations detined by correspondinginternal addresses, means for obtaining access to said storagelocations, said access means including transducer means cooperating withsaid storage device for sensing signals stored therein and means forcontrolling said transducer means to cooperate with selected portions ofsaid storage device, said access means being arranged to control lsaidtransducer means to cooperate with said iirst and second portions forsensing internal address signals and the corresponding external addresssignals simultaneously, an external address register, means for enteringexternal address signals in said register, means for comparing sensedexternal address signals with the condition of said register, saidaccess means being responsive `to a comparison in said comparing meansfor controlling said transducer means to cooperate with said thirdportion for sensing signals in a selected general storage locationdetermined by sensed internal address signals corresponding to sensedexternal address signals etecting a comparison.

3. The invention set forth in claim 2 with the further provision of aninternal address register for indicating a new internal address andmeans responsive to a failure of comparison for recording signalsrepresentative of the condition of said external address register `andthe condition of said internal address register in storage locations ofsaid first and second portions according to the condition of Saidinternal address register.

4. The invention set forth in claim 3 wherein the condition of saidinternal address register is advanced to ,i indicate the next newinternal address available in respense to the operation of saidrecording means.

A5. A decoding device comprising a memory having a first portion forstoring signals representative of external addresses and a secondportion for storing signals representative of corresponding internaladdresses, a lirst register for indicating input external addresses,means for scanning -storage locations in said first and second por-vtions, a second register for indicating an unused internal addresslocation, means for counting scanned storage locations, means forcomparing the condition .of said .counting means with the condition ofsaid second regis- IQIT, means associated with said comparing means lforgenerating a signal in response to the condition of said counting meanscomparing with the condition of said second register, and meansresponsive to said generated vtlglial for recording -in said iirstportion signals deternrinedby 'the Condition ofv said rst register andfor recording in said second portion signals corresponding .t9thecondition of said second register.

6. A storage device wherein access to information stored irlv specificgeneral storage locations is controlled ,by internal address signalsderived from external address Vsignals supplied to the device,comprising a storage medium having a 'plnrality Vof general storagelocations, a plurality Of internal address storage locations and aplurality of, external address storagelocations, means for enteringexternal address signals and .the corresponding internal address signalswhich deiinevarious general storage loca- ;ns in saidV external andinternal address storage locations, sensing means for selectivelyscanning said storage medium, isaidv means being adapted when scanningsaid external address storage locations to simultaneouslyl scan .saidinternal. address `storage locations and sense stored .external addressVsignals and the corresponding internal j,

address signals simultaneously, an external address register, saidregister being settable according to the external address of. generalvstorage locations to which access is desired, means for initiating anaccess operation, said means controlling said sensing means to scan saidinternal andv external address storage locations, a buier register, acomparison circuit associated with said external' address register andYsaid sensing means for comparing the condition ofsaid external addressregister with ,sensed external addressV signals, means responsive to acomparison between signals set in said register and said sensed signalsfor entering the sensed internal' address signals corresponding to theexternal address signals causing. the Vcomparison into said buerregister, and meansiresponsive to the condition of said -buer registerAfor `controlling said sensing means to scan aselected general. storagelocation which corresponds to the condition of saidexternal. addressregister,

'ZL A storage device having a plurality of data storage vlocationsaccessible under controlof a first register for receiving internaladdress information which deiines se- I'ected data storage locations andaddressable under control of a second register for receiving `externaladdress information which does not dene data storage locations,including a plurality of internal address storage locations for storinginformation representative of internal ad.- dresses defining saidplurality of data storage locations.; a plurality of external addressstorage locations for `storing information representative of externaladdresses,- information represcntative of each external address beingstored in a storage location relating to the storage location in whichthe corresponding internal address information is stored, means for.scanning related external and internal address storage locationssimultaneously, means responsive to `scanned external laddressinformation which corresponds to external address information in saidsecond register for entering the related scanned internal addressinformation in said first register, and means re.- sponsive to saidfirst register for controlling access Vto e selected data storagelocation in accordance with the sig,- nals stored in said lirstregister.

8. A memory comprising a storage medium having first portion including aplurality of storage locations for `storing signals representative ofexternal addresses and a second portion including a plurality of storagelocations for storing signals representative Vof respective interna-laddress forms .of said external addresses; means for simultaneouslyscanning the storage locations of Vsa-id first and second portions;lmeans associated with said scanning means for sensi-ng signals storedin t-he scannedA storage locations; means lfor indicating; inputexternaladdress signalls', rst comparison means .connected to saidindicating means and said sensing means. forsgeneratinga signalindicative of an identity between the signals stored in said indicatingmeans and the sign-als sensed in the locations of said first portion andfor generating a signal indicative of a lackof identity should noneexist when all storage locations have been Vscanned by said scanningmeans; means for counting locations scanned; a storage locationregister; second comparison means associated with said counting meansand said storage location register; and recording means responsive' tothe signal indicating,v a lack of identity from Isaidfirst comparisonmeans for recording'- signals indicated by' said indicating means andsaid storage'v location'- register in' response fo said( secondcomparison means indicating an identity between said counting meansandsaidv storage location register.

References' Cited in the file of this' patent UNITED .STATES PATENTS2,611,813 Sharples's etal. Sept. 23, 1,952 2,680,155 M'olnar A Y Junel,v 1954 2,771,595 Hendrickson Nov. 20, 1956 2,796,597 Poorte June 1S,1957 2,891,238 Nettleton Y June 16', 1959 2,946,044 Bolgiano. July 19,1960

7. A STORAGE DEVICE HAVING A PLURALITY OF DATA STORAGE LOCATIONSACCESSIBLE UNDER CONTROL OF A FIRST REGISTER FOR RECEIVING INTERNALADDRESS INFORMATION WHICH DEFINES SELECTED DATA STORAGE LOCATIONS ANDADDRESSABLE UNDER CONTROL OF A SECOND REGISTER FOR RECEIVING EXTERNALADDRESS INFORMATION WHICH DOES NOT DEFINE DATA STORAGE LOCATIONS,INCLUDING A PLURALITY OF INTERNAL ADDRESS STORAGE LOCATIONS FOR STORINGINFORMATION REPRESENTATIVE OF INTERNAL ADDRESSES DEFINING SAID PLURALITYOF DATA STORAGE LOCATIONS; A PLURALITY OF EXTERNAL ADDRESS STORAGELOCATION FOR STORING INFORMATION REPRESENTATIVE OF EXTERNAL ADDRESSES,INFORMATION REPRESENTATIVE OF EACH EXTERNAL ADDRESS BEING STORED IN ASTORAGE LOCATION RELATING TO THE STORAGE LOCATION IN WHICH THECORRESPONDING INTERNAL ADDRESS INFORMATION IS STORED, MEANS FOR SCANNINGRELATED EXTERNAL AND INTERNAL ADDRESS STORAGE LOCATIONS SIMULTANEOUSLY,MEANS RESPONSIVE TO SCANNED EXTERNAL ADDRESS INFORMATION WHICHCORRESPONDS TO EXTERNAL ADDRESS INFORMATION IN SAID SECOND REGISTER FORENTERING THE RELATED SCANNED INTERNAL ADDRESS INFORMATION IN SAID FIRSTREGISTER, AND MEANS RESPONSIVE TO SAID FIRST REGISTER FOR CONTROLLINGACCESS TO A SELECTED DATA STORAGE LOCATION IN ACCORDANCE WITH THESIGNALS STORED IN SAID FIRST REGISTER.